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TC58FVT160/B160AFT/AXB-70,-10
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
16-MBIT (2M x 8 BITS / 1M x 16 BITS) CMOS FLASH MEMORY DESCRIPTION
The TC58FVT160/B160A is a 16,777,216-bit, 3.0-V read-only electrically erasable and programmable flash memory organized as 2,097,152 words x 8 bits or as 1,048,576 words x 16 bits. The TC58FVT160/B160A features commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip.
FEATURES
* * * * Power supply voltage VDD = 2.7 V~3.6 V Operating temperature Ta = -40C~85C Organization 2M x 8 bits / 1M x 16 bits Functions Auto Program, Auto Erase Fast Program Mode Program Suspend/Resume Erase Suspend/Resume data polling / Toggle bit block protection Automatic Sleep, support for hidden ROM area common flash memory interface (CFI) Byte/Word Modes * * * * * * Block erase architecture 1 x 16 Kbytes / 2 x 8 Kbytes 1 x 32 Kbytes / 31 x 64 Kbytes Boot block architecture TC58FVT160AFT/AXB: top boot block TC58FVB160AFT/AXB: bottom boot block Mode control Compatible with JEDEC standard commands Erase/Program cycles 105 cycles typ. Access time 70 ns (CL: 30 pF) 100 ns (CL: 100 pF) Power consumption 5 A (Standby) 30 mA (Read operation) 15 mA (Program/Erase operations) Package TSOPI48-P-1220-0.50 (weight: 0.51 g) P-TFBGA48-0608-0.80AZ (weight: TBD)
*
PIN ASSIGNMENT (TOP VIEW) TC58FVT160/B160AFT
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RESET NC NC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PIN NAMES
A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 A-1, A0~A19 DQ0~DQ15
CE OE
Address Input Data Input/Output Chip Enable Input Output Enable Input Word/Byte Select Input Write Enable Input Ready/Busy Output Hardware Reset Input Not Connected Power Supply Ground
BYTE WE RY/BY
RESET
NC VDD VSS
000707EBA2
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.
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PIN ASSIGNMENT (TOP VIEW)
1 A B C D E F G H A3 A4 A2 A1 A0 C OE VSS 2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 3
TC58FVT160/B160AXB
4 5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 6 A13 A12 A14 A15 A16 BYTE DQ15 VSS
RY/BY
NC A18 NC DQ2 DQ10 DQ11 DQ3
WE
RESET NC A19 DQ5 DQ12 VDD DQ4
000707EBA2
* The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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TC58FVT160/B160AFT/AXB-70,-10
BLOCK DIAGRAM
RY / BY DQ0 VDD VSS RY / BY DQ15
Buffer
I/O Buffer
WE tOEHP
RESET
Control Circuit Command Register
Auto Sequence Control Circuit
Program Circuit
Erase Circuit
Data Latch
CE OE
CE , OE
Control Circuit Column Decoder & Sense Amp
A0
A d d r e s s B u ff e r
A ddress Latch
R o w D ecoder
Memory Cell Array
A19 A-1
Erase Block Decoder
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MODE SELECTION
BYTE MODE MODE Read ID Read (Manufacturer Code) ID Read (Device Code) Standby Output Disable Write Block Protect 1 Verify Block Protect Temporary Block Unprotect Hardware Reset / Standby
CE OE
WORD MODE DQ0~DQ15 DOUT Code Code High-Z High-Z DIN * Code * High-Z
WE H H H * H
(2) (2)
A9 A9 VID VID * * A9 VID VID * *
A6 A6 L L * * A6 L L * *
A1 A1 L L * * A1 H H * *
A0 A0 L H * * A0 L L * *
RESET
DQ0~DQ7 DOUT Code Code High-Z High-Z DIN * Code * High-Z
(1)
L L L H * L L L * *
L L L * H H VID L * *
H H H H * H H H VID L
H * *
Notes: * = VIH or VIL, L = VIL, H = VIH (1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode. Addresses are A19~A0 in Word Mode ( BYTE = VIH), A19~A-1 in Byte Mode ( BYTE = VIL). (2) Pulse input
ID CODE TABLE
CODE TYPE Manufacturer Code TC58FVT160A Device Code TC58FVB160A Verify Block Protect * BA
(2)
A19~A12 * *
A6 L L L L
A1 L L L H
A0 L H H L
CODE (HEX) 0098H 00C2H 0043H Data
(3)
(1)
Notes: * = VIH or VIL, L = VIL, H = VIH (1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode. (2) BA: Block Address (3) 0001H - Protected Block 0000H - Unprotected Block
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COMMAND SEQUENCES
BUS COMMAND SEQUENCE WRITE CYCLES REQ'D Read/Reset Read/Reset Word Byte ID Read Word Byte Auto-Program Word Byte Program Suspend 1 4 3 1 3 Addr. XXXH 555H AAAH 555H AAAH 555H AAAH VIH or VIL VIH or VIL 555H AAAH 6 555H AAAH 1 VIH or VIL VIH or VIL XXXH 555H AAAH 3 2 2 3 555H AAAH XXXH XXXH 555H AAAH 4 555H AAAH 6 555H AAAH 4 555H AAAH 2 55H AAH 98H AAH AAH AAH A0H 90H AAH AAH B0H AAH B0H AAH AAH Data F0H AAH 2AAH 555H 2AAH 555H 2AAH 555H 55H 55H 55H 555H AAAH 555H AAAH 555H AAAH A0H PA
(5)
FIRST BUS WRITE CYCLE
SECOND BUS WRITE CYCLE Addr. Data
THIRD BUS WRITE CYCLE Addr. Data
FOURTH BUS WRITE CYCLE Addr. Data
FIFTH BUS WRITE CYCLE Addr. Data
SIXTH BUS WRITE CYCLE Addr. Data
F0H
RA
(1)
RD
(2)
90H
IA
(3)
ID
(4)
PD
(6)
Program Resume Auto Chip Erase Auto Block Erase Word Byte Word Byte
1
30H 2AAH 555H 2AAH 555H 55H 555H AAAH 555H AAAH 80H 555H AAAH 555H AAAH AAH 2AAH 555H 2AAH 555H 55H 555H AAAH BA
(7)
6
AAH
55H
80H
AAH
55H
10H
30H
Block Erase Suspend
Block Erase Resume Block Protect 2 Verify Block Protect Fast Program Set Fast Program Fast Program Reset Hidden ROM Mode Entry Hidden ROM Program Hidden ROM Erase Hidden ROM Mode Exit Query Command Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
1 4 3
30H 60H AAH BPA
(8)
60H 55H
XXXH 555H AAAH
40H 90H
BPA BPA
(8) (8)
BPD BPD
(9) (9)
2AAH 555H 2AAH 555H PA
(5)
55H PD F0H
(6)
555H AAAH
20H
XXXH 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H CA
(10)
(12)
55H
555H AAAH
88H
(5) (6)
55H
555H AAAH
A0H
PA
PD
55H
555H AAAH
80H
555H AAAH
AAH
2AAH 555H
55H
BA
(7)
30H
55H
(11)
555H AAAH
90H
XXXH
00H
CD
Notes: The system should generate the following address patterns: Word Mode: 555H or 2AAH on address pins A10~A0 Byte Mode: AAAH or 555H on address pins A10~A-1 DQ8~DQ15 are ignored in Word Mode. (1) RA: Read Address (7) BA: Block Address = A19~A12 (2) RD: Read Data (8) BPA: Block Address and ID Read Address (A6, A1, A0) (3) IA: ID Read Address (A6, A1, A0) Block Address = A19~A12 Manufacturer Code = (0, 0, 0) ID Read Address = (0, 1, 0) Device Code = (0, 0, 1) (9) BPD: Verify Data (4) ID: ID Data (10) CA: CFI Address (5) PA: Program Address (11) CD: CFI Data (6) PD: Program Data (12) F0H: 00H is valid too
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OPERATION MODES
In addition to the Read, Write and Erase Modes, the TC58FVT160/B160A features many functions including block protection and data polling. When incorporating the device into a deign, please refer to the timing charts and flowcharts in combination with the description below.
READ MODE
To read data from the memory cell array, set the device to Read Mode. In Read Mode the device can perform high-speed random access as asynchronous ROM. The device is automatically set to Read Mode immediately after power-on or on completion of automatic operation. A software reset releases ID Read Mode and the lock state which the device enters if automatic operation ends abnormally, and sets the device to Read Mode. A hardware reset terminates operation of the device and resets it to Read Mode. When reading data without changing the address immediately after power-on, either input a hardware Reset or change CE from H to L.
ID Read Mode
ID Read Mode is used to read the device maker code and device code. The mode is useful in that it allows EPROM programmers to identify the device type automatically. ID read can be executed in two ways, as follows: (1) Applying VID to A9 This method is used mainly by EPROM programmers. Applying VID to A9 sets the device to ID Read Mode, outputting the maker code from address 00H and the device code from address 01H. Releasing VID from A9 returns the device to Read Mode. (2) Input command sequence Inputting an ID Read command sets to ID Read Mode. The maker code is output from address 00; the device code is output from address 01. Inputting a Reset command releases ID Read Mode and returns the device to Read Mode. Access time in ID Read Mode is the same as that in Read Mode. For a list of the codes, please refer to the ID Code Table.
Standby Mode
There are two ways to put the device into Standby Mode. (1) Control using CE and RESET With the device in Read Mode, input VDD 0.3 V to CE and RESET . The device will enter Standby Mode and the current will be reduced to the standby current (IDDS1). (2) Control using RESET only With the device in Read Mode, input VSS 0.3 V to RESET . The device will enter Standby Mode and the current will be reduced to the standby current (IDDS1). In Standby Mode DQ is put in High-Impedance state.
Auto-Sleep Mode
This function suppresses power dissipation during reading. If the address input does not change for 150 ns, the device will automatically enter Sleep Mode and the current will be reduced to the standby current (IDDS2). Because the output data is latched, data is output in Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new address is output.
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Output Disable Mode
Inputting VIH to OE disables output from the device and sets DQ to High-Impedance.
Command Write
The TC58FVT160/B160A uses the standard JEDEC control commands for a single-power supply E2PROM. A Command Write is executed by inputting the address and data into the Command Register. The command is written by inputting a pulse to WE with CE = VIL and OE = VIH ( WE control). The command can also be written by inputting a pulse to CE with WE = VIL ( CE control). The address is latched on the falling edge of either WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are valid for data input and DQ8~DQ15 are ignored. To abort input of the command sequence use the Reset command. The device will reset the Command Register and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device will enter Read Mode.
Software Reset
Apply a software reset by inputting a Read/Reset command. A software reset returns the device from ID Read Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and clears the Command Register.
Hardware Reset
A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for tRP, the device abandons the operation which is in progress and enters Read Mode after tREADY. Note that if a hardware reset is applied during data overwriting, such as a Write or Erase operation, data at the address or block being written to at the time of the reset will become undefined. After a hardware reset the device enters Read Mode if RESET = VIH or Standby Mode if RESET = VIL. The DQ pins are High-Impedance when RESET = VIL. After the device has entered Read Mode, Read operations and input of any command are allowed.
Comparison between Software Reset and Hardware Reset
ACTION Releases ID Read Mode or CFI Mode. Clears the Command Register. Releases the lock state if automatic operation has ended abnormally. Stops any automatic operation which is in progress. Stops any operation other than the above and returns the device to Read Mode. SOFTWARE RESET True True True False False HARDWARE RESET True True True True True
BYTE/Word Mode
BYTE is used select Word Mode (16 bits) or Byte Mode (8 bits) for the TC58FVT160/B160A. If VIH is input to BYTE , the device will operate in Word Mode. Read data or write commands using DQ0~DQ15. When VIL is input to BYTE , read data or write commands using DQ0~DQ7. DQ15/A-1 is used as the lowest address. DQ8~DQ14 will become High-Impedance.
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Auto-Program Mode
The TC58FVT160/B160A can be programmed in either byte or word units. Auto-Program Mode is set using the Program command. The program address is latched on the falling edge of the WE signal and data is latched on the rising edge of the fourth Bus Write cycle (with WE control). Auto programming starts on the rising edge of the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To read the Hardware Sequence flag, specify the address to which the Write is being performed. During Auto-Program execution, a command sequence cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is terminated in this manner, the data written so far is invalid. Any attempt to program a protected block is ignored. In this case the device enters Read Mode 3 s after the rising edge of the WE signal in the fourth Bus Write cycle. If an Auto-Program operation fails, the device remains in the programming state and does not automatically return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails, the block which contains the address to which data could not be programmed should not be used. The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device error. A cell containing 0 must be erased in order to set it to 1.
Fast Program Mode
Fast Program is a function which enables execution of the command sequence for the Auto Program to be completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires four cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the Fast Program command. Write in this mode uses the Fast Program command but operation is the same at that for ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read operations can be performed as usual. To exit this mode, the Fast Program Reset command must be input. When the command is input, the device will return to Read Mode.
Program Suspend/Resume Mode
Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but ignores the command in other modes. After input of the command, the device will enter Program Suspend Read Mode after tSUSP. During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are the same as usual. After completion of Program Suspend input a Program Resume command to return to Write Mode. On receiving the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the bank to which data is being written. Program Suspend can be run in Fast Program Mode.
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Auto Chip Erase Mode
The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the Hardware Sequence flag. Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional Erase operation must be performed. Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed and the device will enter Read mode 100 s after the rising edge of the WE signal in the sixth bus cycle. If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take measures to prevent subsequent use of the failed block.
Auto Block Erase / Auto Multi-Block Erase Modes
The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The block address is latched on the falling edge of the WE signal in the sixth bus cycle. The block erase starts as soon as the Erase Hold Time (tBEH) has elapsed after the rising edge of the WE signal. When multiple blocks are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the device will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive rising edge of WE . Once operation starts, all memory cells in the selected block are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which auto-erase operation is being performed must be specified. All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing. Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase operation is not executed and the device returns to Read Mode 100 s after the rising edge of the WE signal in the last bus cycle. If an auto-erase operation fails, the device remains in Erasing state and does not return to Read Mode. The device status is indicated by the Hardware Sequence flag. After a failure either a Reset command or a Hardware Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take measures to prevent subsequent use of the failed block.
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Erase Suspend / Erase Resume Modes
Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block. The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes . In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after tSUSE. The device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output will stop toggling and RY/ BY will be set to High-Impedance. Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not been selected for the Auto Block Erase. Data is written in the usual manner. To resume the Auto Block Erase, input an Erase Resume command. On receiving an Erase Resume command, the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend command is input during the Erase Hold Time, the device will return to the state it was in at the start of the Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on RY/ BY .
Block Protection
Block Protection is a function for disabling writing and erasing specific blocks. Block protection can be carried out in two ways: by supplying a high voltage (VID) to the device (see Block protection 1) or by supplying a high voltage and a command sequence (see Block protection 2). (1) Block protection 1 Specify a device block address and make the following signal settings A9 = OE = VID, A1 = VIH and CE = A0 = A6 = VIL. Now when a pulse is input to WE for tPPLH, the device will start to write to the block protection circuit. Block protection can be verified using the Verify Block Protect command. Inputting VIL on OE sets the device to Verify Mode. 01H is output if the block is protected and 00H is output if the block is unprotected. If block protection was unsuccessful, the operation must be repeated. Releasing VID from A9 and OE terminates this mode. (2) Block protection 2 Applying VID to RESET and inputting the Block Protect 2 command also performs block protection. The first cycle of the command sequence is the Set-up command. In the second cycle, the Block Protect command is input, in which a block address and A1 = VIH and A0 = A6 = VIL are input. Now the device writes to the block protection circuit. There is a wait of tPPLH until this write is completed; however, no intervention is necessary during this time. In the third cycle the Verify Block Protect command is input. This command verifies the write to the block protection circuit. Read is performed in the fourth cycle. If the protection operation is complete, 01H is output. If a value other than 01H is output, block protection is not complete and the Block Protect command must be input again. Removing the VID input from RESET exits this mode.
Temporary Block Unprotection
The TC58FVT160/B160A has a temporary block unprotection feature which disables block protection for all protected blocks. Unprotection is enabled by applying VID to the RESET pin. Now Write and Erase operations can be performed on all blocks. The device returns to its previous state when VID is removed from the RESET pin. That is, previously protected blocks will be protected again.
Verify Block Protect
The Verify Block Protect command is used to ascertain whether a block is protected or unprotected. Verification is performed either by inputting the Verify Block Protect command or by applying VID to the A9 pin, as for ID Read Mode, and setting the block address = A0 = A6 = VIL and A1 = VIH. If the block is protected, 01H is output. If the block is unprotected, 00H is output.
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Hidden ROM Area
The TC58FVT160/B160A features a 64-Kbyte hidden ROM area which is separate from the memory cells. The area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot be released, once the block is protected, data in the block cannot be overwritten. The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations are the same as auto operations except that the device is in Hidden ROM Mode. To protect the hidden ROM area, use the block protection function. The operation of Block Protect here is the same as a normal Block Protect except that VIH rather than VID is input to RESET . Once the block has been protected, protection cannot be released, even using the temporary block unprotection function. Use Block Protect carefully. To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read Mode.
HIDDEN ROM AREA ADDRESS TABLE
TYPE BOOT BLOCK ARCHITECTURE TOP BOOT BLOCK BOTTOM BOOT BLOCK BYTE MODE ADDRESS RANGE 1F0000H~1FFFFFH 000000H~00FFFFH SIZE 64 Kbytes 64 Kbytes WORD MODE ADDRESS RANGE F8000H~FFFFFH 000000H~007FFFH SIZE 32 Kwords 32 Kwords
TC58FVT160A TC58FVB160A
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COMMON FLASH MEMORY INTERFACE (CFI)
The TC58FVT160/B160A conforms to the CFI specifications. To read information from the device, input the Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the Reset command.
CFI CODE TABLE
ADDRESS A6~A0 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH DATA DQ15~DQ0 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H DESCRIPTION
ASCII string "QRY"
Primary OEM command set 2: AMD/FJ standard type Address for primary extended table Alternate OEM command set 0: none exists Address for alternate OEM extended table VDD (min) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VDD (max) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VPP (min) voltage VPP (max) voltage Typical time-out per single byte/word write (2 s) Typical time-out for minimum size buffer write (2 s) Typical time-out per individual block erase (2 ms) Typical time-out for full chip erase (2 ms) Maximum time-out for byte/word write (2 times typical) Maximum time-out for buffer write (2 times typical) Maximum time-out per individual block erase (2 times typical) Maximum time-out for full chip erase (2 times typical) Device Size (2 byte) Flash device interface description 2: x8/x16 Maximum number of bytes in multi-byte write (2 )
N N N N N N N N N N
1BH
0027H
1CH
0036H
1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH
0000H 0000H 0004H 0000H 000AH 0000H 0005H 0000H 0004H 0000H 0015H 0002H 0000H 0000H 0000H
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ADDRESS A6~A0 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 40H 41H 42H 43H 44H DATA DQ15~DQ0 0004H 0000H 0000H 0040H 0000H 0001H 0000H 0020H 0000H 0000H 0000H 0080H 0000H 001EH 0000H 0000H 0001H 0050H 0052H 0049H 0031H 0031H DESCRIPTION Number of erase block regions within device Erase Block Region 1 information Bits 0~15: y = block number Bits 16~31: z = block size (z x 256 bytes)
Erase Block Region 2 information
Erase Block Region 3 information
Erase Block Region 4 information
ASCII string "PRI"
Major version number, ASCII Minor version number, ASCII Address-Sensitive Unlock 0: Required 1: Not required Erase Suspend 0: Not supported 1: For Read-only 2: For Read & Write Block Protect 0: Not supported X: Number of blocks per group Block Temporary Unprotect 0: Not supported 1: Supported Block Protect/Unprotect scheme Simultaneous operation 0: Not supported 1: Supported Burst Mode 0: Not supported Page Mode 0: Not supported Top/Bottom Boot Block Flag 2: TC58FVB160 3: TC58FVT160 Program suspend 0: Not supported 1: Supported
45H
0000H
46H
0002H
47H
0001H
48H
0001H
49H
0004H
4AH
0000H
4BH
0000H
4CH
0000H
4FH
000XH
50H
0001H
2001-09-05 13/41
TC58FVT160/B160AFT/AXB-70,-10
HARDWARE SEQUENCE FLAGS
The TC58FVT160A/B160A has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when CE = OE = VIL in Read Mode. The RY/ BY output can be either High or Low. The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The Hardware Sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data.
STATUS Auto Programming Read in Program Suspend
(1)
DQ7
DQ 7
DQ6 Toggle Data Toggle Toggle Toggle Toggle 1 Data Toggle Toggle Toggle Toggle Toggle
DQ5 0 Data 0 0 0 0 0 Data 0 0 1 1 1
DQ3 0 Data 0 0 1 1 0 Data 0 0 0 1 0
DQ2 1 Data Toggle 1 Toggle 1 Toggle Data Toggle 1 1 NA NA
RY/BY 0 High-Z 0 0 0 0 High-Z High-Z 0 0 0 0 0
Data Selected
(2) (3)
0 0 0 0 1 Data
DQ 7 DQ 7 DQ 7
Erase Hold Time In Auto Erase In Progress Auto Erase Selected
Not-selected
Not-selected Selected Read In Erase Suspend Programming Not-selected Auto Programming Time Limit Exceeded Auto Erase Programming in Erase Suspend Not-selected Selected
0
DQ 7
Notes: DQ outputs cell data and RY/BY goes High-Impedence when the operation has been completed. DQ0 and DQ1 pins are reserved for future use. 0 is output on DQ0, DQ1 and DQ4. (1) Data output from an address to which Write is being performed is undefined. (2) Output when the block address selected for Auto Block Erase is specified and data is read from there. During Auto Chip Erase, all blocks are selected. (3) Output when a block address not selected for Auto Block Erase and data is read from there.
DQ7 ( DATA polling)
During an Auto-Program or auto-erase operation, the device status can be determined using the data polling function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation, DQ7 outputs inverted data during the programming operation and outputs actual data after programming has finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data. When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE signal.
2001-09-05 14/41
TC58FVT160/B160AFT/AXB-70,-10
DQ6 (Toggle bit 1)
The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately outputs a 0 or a 1 for each OE access while CE = VIL while the device is busy. When the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the operation fails, the DQ6 output toggles. If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around 3 s. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block, DQ6 will toggle for around 100 s. It will then stop toggling. After toggling has stopped the device will return to Read Mode.
DQ5 (internal time-out)
If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the operation has not been completed within the allotted time. Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case DQ5 outputs a 1. Either a hardware reset or a software Reset command is required to return the device to Read Mode.
DQ3 (Block Erase timer)
The Block Erase operation starts 50 s (the Erase Hold Time) after the rising edge of WE in the last command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time. Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.
DQ2 (Toggle bit 2)
DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the device is in Erase Suspend Mode. If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle. Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2 output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in Programming Mode, DQ2 will output a 1.
RY/BY (READY/ BUSY )
The TC58FVT160A/B160A has a RY/ BY signal to indicate the device status to the host processor. A 0 (Busy state) indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates that the operation has finished and that the device can now accept a new command. RY/ BY outputs a 0 when an operation has failed. RY/ BY outputs a 0 after the rising edge of WE in the last command cycle. During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/ BY outputs a 1 during an Erase Suspend operation. The output buffer for the RY/ BY pin is an open-drain type circuit, allowing a wired-OR connection. A pull-up resistor must be inserted between VDD and the RY/ BY pin.
2001-09-05 15/41
TC58FVT160/B160AFT/AXB-70,-10
DATA PROTECTION
The TC58FVT160/B160A includes a function which guards against malfunction or data corruption.
Protection against Program/Erase Caused by Low Supply Voltage
To prevent malfunction at power-on or power-down, the device will not accept commands while VDD is below VLKO. In this state, command input is ignored. If VDD drops below VLKO during an Auto Operation, the device will terminate Auto-Program execution. In this case, Auto operation is not executed again when VDD return to recommended VDD voltage Therefore, command need to be input to execute Auto operation again. When VDD > VLKO, make up countermeasure to be input accurately command in system side please.
Protection against Malfunction Caused by Glitches
To prevent malfunction during operation caused by noise from the system, the device will not accept pulses shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the glitch is input to the device malfunction may occur. The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a proper command is input, the device may not operate. To avoid this possibility, clear the Command Register before command input. In an environment prone to system noise, Toshiba recommend input of a software or hardware reset before command input.
Protection against Malfunction at Power-on
To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE = VIL and OE = VIL, the device does not latch the command on the first rising edge of WE or CE . Instead, the device automatically Resets the Command Register and enters Read Mode.
2001-09-05 16/41
TC58FVT160/B160AFT/AXB-70,-10
ABSOLUTE MAXIMUM RATINGS
SYMBOL VDD VIN VDQ VIDH PD TSOLDER TSTG TOPR IOSHORT VDD Supply Voltage Input Voltage Input/Output Voltage Maximum Input Voltage for A9, OE and RESET Power Dissipation Soldering Temperature (10 s) Storage Temperature Operating Temperature Output Short-Circuit Current
(1)
PARAMETER
RANGE -0.6~4.6 -0.6~VDD + 0.5 ( 4.6) -0.6~VDD + 0.5 ( 4.6) 13.0 126 260 -55~150 -40~85 100
UNIT V V V V mW C C C mA
(1) Outputs should be shorted for no more than one second. No more than one output should be shorted at a time.
CAPACITANCE (Ta = 25C, f = 1 MHz)
TSOPI
SYMBOL CIN COUT CIN2 Input Pin Capacitance Output Pin Capacitance Control Pin Capacitance PARAMETER CONDITION VIN = 0 V VOUT = 0 V VIN = 0 V MAX 4 8 7 UNIT pF pF pF
This parameter is periodically sampled and is not tested for every device.
TFBGA
SYMBOL CIN COUT CIN2 Input Pin Capacitance Output Pin Capacitance Control Pin Capacitance PARAMETER CONDITION VIN = 0 V VOUT = 0 V VIN = 0 V MAX TBD TBD TBD UNIT pF pF pF
This parameter is periodically sampled and is not tested for every device.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL VDD VIH VIL VID Ta VDD Supply Voltage Input High-Level Voltage Input Low-Level Voltage High-Level Voltage for A9, OE and RESET Operating Temperature PARAMETER MIN 2.7 0.7 x VDD -0.3
(1)
MAX 3.6 VDD + 0.3
(2)
UNIT
V
0.2 x VDD 12.6 85 C
11.4 -40
(1) -2 V (pulse width of 20 ns max) (2) +2 V (pulse width of 20 ns max)
2001-09-05 17/41
TC58FVT160/B160AFT/AXB-70,-10
DC CHARACTERISTICS
SYMBOL ILI ILO VOH VOL IDDO1 IDDO2 IDDO3 IDDO4 IDDS1 IDDS2 IID VLKO PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VDD Average Read Current VDD Average Program Current VDD Average Erase Current VDD Average Program-whileErase-Suspend Current VDD Standby Current VDD Standby Current (1) (Automatic Sleep Mode ) High-Voltage Input Current for A9, OE and RESET Low-VDD Lock-out Voltage CONDITION 0 V VIN VDD 0 V VOUT VDD IOH = -0.1 mA IOH = -2.5 mA IOL = 4.0 mA VIN = VIH/VIL, IOUT = 0 mA tCYCLE = tRC = 100 ns VIN = VIH/VIL, IOUT = 0 mA VIN = VIH/VIL, IOUT = 0 mA VIN = VIH/VIL, IOUT = 0 mA
CE = RESET = VDD or RESET = VSSV
MIN VDD - 0.4 0.85 x VDD 2.3
MAX 1 1 0.4 30 15
UNIT A
V
mA 15 15
5 A
VIH = VDD VIL = VSS 11.4 V VID 12.6 V
5
35 2.5 V
(1) The device enters Automatic Sleep Mode in which the address remains fixed for during 150 ns.
AC TEST CONDITIONS
PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) Timing Measurement Reference Level (input) Timing Measurement Reference Level (output) Output Load CONDITION VDD, 0.0 V 5 ns 1.5 V, 1.5 V 1.5 V, 1.5 V CL (100 pF) + 1 TTL Gate/ CL (30 pF) + 1 TTL Gate
2001-09-05 18/41
TC58FVT160/B160AFT/AXB-70,-10
AC CHARACTERISTICS AND OPERATING CONDITIONS
READ CYCLE
PRODUCT NAME OUTPUT CAPACITANCE LOAD (CL) SYMBOL tRC tACC tCE tOE tCEE tOEE tOH tDF1 tDF2 Read Cycle Time Address Access Time
CE Access Time OE Access Time CE to Output Low-Z OE to Output Low-Z
-70 30 pF MIN 70 0 0 0 MAX 70 70 30 20 20 MIN 80 0 0 0 100 pF MAX 80 80 35 25 25
-10
PARAMETER
MIN 100 0 0 0
MAX UNIT 100 100 40 30 30 ns ns ns ns ns ns ns ns ns
Output Data Hold Time
CE to Output High-Z OE to Output High-Z
BLOCK PROTECT
SYMBOL tVPT tVPS tCESP tVPH tPPLH VID Transition Time VID Set-up Time
CE Set-up Time OE Hold Time
PARAMETER
MIN 4 4 4 4 100
MAX
UNIT s s s s s
WE Low-Level Hold Time
PROGRAM AND ERASE CHARACTERISTICS
SYMBOL tPPW Auto-Program Time (Word Mode) tPCEW tPBEW tEW Auto Chip Erase Time Auto Block Erase Time Erase/Program Cycle PARAMETER Auto-Program Time (Byte Mode) MIN 10
5
TYP. 8 11 25 0.7
MAX 300 300 350 10
UNIT s s s s Cycles
2001-09-05 19/41
TC58FVT160/B160AFT/AXB-70,-10
COMMAND WRITE/PROGRAM/ERASE CYCLE
SYMBOL PARAMETER MIN tCMD
tAS
-70 MAX 90 20 30 1.5 1 15 1 MIN 100 0 50 20 50 0 50 20 0 0 50 20 20 0 0 0 90 20 50 500 500 0 50 5
-10 MAX 90 20 30 1.5 1 15 1
UNIT
Command Write Cycle Time Address Set-up Time / BYTE Set-up Time Address Hold Time / BYTE Hold Time Address Hold Time from WE High level Data Set-up Time Data Hold Time WE Low-Level Hold Time WE High-Level Hold Time
CE Set-up Time to WE Active CE Hold Time from WE High Level CE Low-Level Hold Time CE High-Level Hold Time CE Hold Time from WE High Level
70 0 35 20 35 0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns s ns ns ns ns s s s s
tAH tAHW tDS tDH tWELH tWEHH tCES tCEH tCELH tCEHH tCHW tWES tWEH tOES tOEHP tOEHT tBEH tVDS tBUSY tRP tREADY tRB tRH tCEBTS tBTD tSUSP tRESP tSUSE tRESE
( WE Control) ( WE Control)
( WE Control) ( WE Control) ( CE Control) ( CE Control)
35 20 0 0 35 20 20
WE Set-up time to CE Active WE Hold Time from CE High Level
OE Set-up Time OE Hold Time (Toggle, Data Polling) OE High-Level Hold Time (Toggle)
( CE Control) ( CE Control)
0 0 0 90 20 50 500 500 0 50 5
Erase Hold Time VDD Set-up Time Program/Erase Valid to RY/BY Delay
RESET Low-Level Hold Time RESET Low-Level to Read Mode
RY/BY Recovery Time
RESET Recovery Time CE Set-up time BYTE Transition
BYTE to Output High-Z Program Suspend Command to Suspend Mode Program Resume Command to Program Mode Erase Suspend Command to Suspend Mode Erase Resume Command to Erase Mode
2001-09-05 20/41
TC58FVT160/B160AFT/AXB-70,-10
TIMING DIAGRAMS
VIH or VIL Data invalid
Read / ID Read Operation
tRC Address tACC tCE
CE
tOH
tOE tOEE
OE
tDF1
tCEE WE tOEH
tDF2
DOUT
Hi-Z
Output data valid
Hi-Z
ID Read Operation (apply VID to A9)
tRC A0
A1 tACC A6
VID VIH A9
tVPS tCE
CE
tOE
OE
WE
DOUT Read Mode
Hi-Z
Manufacturer code
Hi-Z
Device code
Hi-Z Read Mode
ID Read Mode
2001-09-05 21/41
TC58FVT160/B160AFT/AXB-70,-10
Command Write Operation
This is the timing of the Command Write Operation. The timing which is described in the following pages is essentially the same as the timing shown on this page. * WE Control
tCMD Address tAS Command address tAH tAHW
CE
tCES
tCEH
WE tWELH tDS DIN tDH tWEHH
Command data
*
CE Control
tCMD Address tAS Command address tAH
CE
tCELH tWES WE tDS DIN tDH tWEH
tCEHH
Command data
2001-09-05 22/41
TC58FVT160/B160AFT/AXB-70,-10
ID Read Operation (input command sequence)
Address
555H tCMD
2AAH
555H
00H tRC
01H
CE
OE
tOES WE
DIN
AAH
55H
90H Manufacturer code Device code
DOUT
Hi-Z Read Mode (input of ID Read command sequence) ID Read Mode
(Continued)
Address
555H tCMD
2AAH
555H
CE
OE
WE
DIN
AAH
55H
F0H
DOUT
Hi-Z ID Read Mode (input of Reset command sequence) Read Mode
Note: Word Mode address shown.
2001-09-05 23/41
TC58FVT160/B160AFT/AXB-70,-10
Auto-Program Operation ( WE Control)
Address
555H tCMD
2AAH
555H
PA
PA
CE
tCHW
OE
tOEHP tOES tPPW
WE
DIN
AAH
55H
A0H
PD
DOUT tVDS VDD Note: Word Mode address shown. PA: Program address PD: Program data
Hi-Z
DQ7
DOUT
Auto Chip Erase / Auto Block Erase Operation ( WE Control)
Address
555H tCMD
2AAH
555H
555H
2AAH
555H/BA
CE
OE
tOES WE
DIN tVDS VDD
AAH
55H
80H
AAH
55H
10H/30H
Note: Word Mode address shown. BA: Block address for Auto Block Erase operation
2001-09-05 24/41
TC58FVT160/B160AFT/AXB-70,-10
Auto-Program Operation ( CE Control)
Address
555H tCMD
2AAH
555H
PA
PA
CE
tPPW
OE
tOEHP tOES
WE
DIN
AAH
55H
A0H
PD
DOUT tVDS VDD Note: Word Mode address shown. PA: Program address PD: Program data
Hi-Z
DQ7
DOUT
Auto Chip Erase / Auto Block Erase Operation ( CE Control)
Address 555H tCMD 2AAH 555H 555H
2AAH
555H/BA
CE
OE
tOES WE
DIN tVDS VDD
AAH
55H
80H
AAH
55H
10H/30H
Note: Word Mode address shown. BA: Block address for Auto Block Erase operation
2001-09-05 25/41
TC58FVT160/B160AFT/AXB-70,-10
Program/Erase Suspend Operation
Address RA
CE
OE
WE tOE DIN B0H tCE DOUT Hi-Z tSUSP/tSUSE RY/BY Program/Erase Mode RA: Read address Suspend Mode DOUT Hi-Z
Program/Erase Resume Operation
Address RA PA/BA
CE
OE
tOES WE tDF1 tDF2 30H
tRESP/tRESE
tOE
DIN
tCE DOUT DOUT Hi-Z Flag Hi-Z
RY/BY Suspend Mode PA: Program address BA: Block address RA: Read address Flag: Hardware Sequence flag Program/Erase Mode
2001-09-05 26/41
TC58FVT160/B160AFT/AXB-70,-10
RY/BY during Auto Program/Erase Operation
CE
Command input sequence
WE tBUSY During operation
RY / BY
Hardware Reset Operation
WE tRB
RESET
tRP tREADY RY/BY
Read after RESET
tRC
Address tRH
RESET
tACC
tOH
DOUT
Hi-Z
Output data valid
2001-09-05 27/41
TC58FVT160/B160AFT/AXB-70,-10
BYTE during Read Operation
CE
tCEBTS
OE
BYTE tBTD DQ0~DQ7 Data Output Data Output
DQ8~DQ14
Data Output tACC
DQ15/A-1
Data Output
Address Input
BYTE during Write Operation
CE
WE tAS BYTE tAH
2001-09-05 28/41
TC58FVT160/B160AFT/AXB-70,-10
Hardware Sequence Flag ( DATA Polling)
Address
Last Command Address tCMD
PA/BA
CE
tCE tOE
OE
tDF1
tOEHP WE tPPW /tPCEW /tPBEW DIN
Last Command Data
tDF2
tACC
tOH
DQ7
DQ7
Valid
Valid
DQ0~DQ6 tBUSY RY/BY PA: Program address BA: Block address
Invalid
Valid
Valid
Hardware Sequence Flag (Toggle bit)
Address
Last Command Address tCMD
PA/BA
CE
tOEHT
OE
tCE
tOEHP
WE
tPPW /tPCEW /tPBEW DIN
Last Command Data
tOE
DQ2/DQ6 tBUSY RY/BY
Toggle
Toggle
Stop* Toggle
Valid
PA: Program address BA: Block address *DQ2/DQ6 stops toggling when auto operation has been completed.
2001-09-05 29/41
TC58FVT160/B160AFT/AXB-70,-10
Block Protect 1 Operation
Block Protect Address BA Verify Block Protect
A0
A1 tVPT A6
VID VIH A9
VID VIH OE
tVPS tPPLH
tVPH tVPH
WE tCESP
CE
tOE
DOUT
Hi-Z
01H*
Hi-Z
BA: Block address *: 01H indicates that block is protected.
2001-09-05 30/41
TC58FVT160/B160AFT/AXB-70,-10
Block Protect 2 Operation
BA + 1
Address tCMD A0
BA tCMD
BA tCMD
BA tRC
A1
A6
CE
OE
tPPLH WE tVPS VID VIH
RESET
DIN
60H
60H
40H tOE
60H
DOUT
Hi-Z
01H*
BA: Block address BA + 1: Address of next block *: 01H indicates that block is protected.
2001-09-05 31/41
TC58FVT160/B160AFT/AXB-70,-10
FLOWCHARTS
Auto Program
Start
Auto-Program Command Sequence (see below)
DATA Polling or Toggle Bit
Address = Address + 1
No
Last Address? Yes Auto Program Completed
Auto-Program Command Sequence (address/data)
555H/AAH
2AAH/55H
555H/A0H
Program Address/ Program Data
Note: The above command sequence takes place in Word Mode.
2001-09-05 32/41
TC58FVT160/B160AFT/AXB-70,-10
Fast Program
Start
Fast Program Set Command Sequence (see below) Fast Program Command Sequence (see below)
DATA Polling or Toggle Bit
Address = Address + 1
No
Last Address? Yes Program Sequence (see below) Fast Program Completed
Fast Program Set Command Sequence (Address/Data) 555H/AAH
Fast Program Command Sequence (Address/Data) XXXH/A0H
Fast Program Reset Command Sequence (Address/Data) XXXH/90H
2AAH/55H
Program Address/ Program Data
XXXH/F0H
555H/20H
Note: The above command sequence takes place in word mode.
2001-09-05 33/41
TC58FVT160/B160AFT/AXB-70,-10
Auto Erase
Start
Auto Erase Command Sequence (see below)
DATA Polling or Toggle Bit
Auto Erase Completed
Auto Chip Erase Command Sequence (address/data)
Auto Block / Auto-Multi Block Erase Command Sequence (address/data)
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Block Address/30H
Block Address/30H
Block Address/30H
Additional address inputs during Auto Multi-Block Erase
Note: The above command sequence takes place in Word Mode.
2001-09-05 34/41
TC58FVT160/B160AFT/AXB-70,-10
DQ7 DATA Polling
Start
Read Byte (DQ0~DQ7) Addr. = VA DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ0~DQ7) Addr. = VA DQ7 = Data? No Fail Pass Yes 1) 1) : DQ7 must be rechecked even if DQ5 = 1 because DQ7 may change at the same time as DQ5. Yes
DQ6 Toggle Bit
Start
Read Byte (DQ0~DQ7) Addr. = VA DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte (DQ0~DQ7) Addr. = VA DQ6 = Toggle? Yes Fail Pass No 1) 1) : DQ6 must be rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time that DQ5 changes to 1. No
VA: Byte address for programming Any of the addresses within the block being erased during a Block Erase operation "Don't care" during a Chip Erase operation Any address not within the current block during an Erase Suspend operation
2001-09-05 35/41
TC58FVT160/B160AFT/AXB-70,-10
Block Protect 1
Start
PLSCNT = 1
Set up Block Address Addr. = BPA
Wait for 4 s
OE = A9 = VID, CE = VIL
Wait for 4 s
WE = VIL
Wait for 100 s
WE = VIH
PLSCNT = PLSCNT + 1
Wait for 4 s
OE = VIH
Wait for 4 s
OE = VIL
Verify Block Protect No Data = 01H? Yes Yes Protect Another Block? No Remove VID from A9 Block Protect Complete No PLSCNT = 25? Yes Device Failed
BPA: Block Address and ID Read Address (A6, A1, A0) ID Read Address = (0, 1, 0)
2001-09-05 36/41
TC58FVT160/B160AFT/AXB-70,-10
Block Protect 2
Start
RESET = VID
Wait for 4 s
PLSCNT = 1
Block Protect 2 Command First Bus Write Cycle (XXXH/60H)
Set up Address Addr. = BPA Block Protect 2 Command Second Bus Write Cycle (BPA/60H)
Wait for 100 s
Block Protect 2 Command Third Bus Write Cycle (XXXH/40H)
PLSCNT = PLSCNT + 1
Verify Block Protect No Data = 01H? Yes Yes Protect Another Block? No Remove VID from RESET Reset Command No PLSCNT = 25? Yes Remove VID from RESET
Reset Command
Device Failed
Block Protect Complete
BPA: Block Address and ID Read Address (A6, A1, A0) ID Read Address = (0, 1, 0)
2001-09-05 37/41
TC58FVT160/B160AFT/AXB-70,-10
BLOCK ERASE ADDRESS TABLES
(1) TC58FVT160A (top boot block)
BLOCK # BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BLOCK ADDRESS A19 A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 1 x BLOCK SIZE (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 ADDRESS RANGE BYTE MODE 00000h~0FFFFh 10000h~1FFFFh 20000h~2FFFFh 30000h~3FFFFh 40000h~4FFFFh 50000h~5FFFFh 60000h~6FFFFh 70000h~7FFFFh 80000h~8FFFFh 90000h~9FFFFh A0000h~AFFFFh B0000h~BFFFFh C0000h~CFFFFh D0000h~DFFFFh E0000h~EFFFFh F0000h~FFFFFh 100000h~10FFFFh 110000h~11FFFFh 120000h~12FFFFh 130000h~13FFFFh 140000h~14FFFFh 150000h~15FFFFh 160000h~16FFFFh 170000h~17FFFFh 180000h~18FFFFh 190000h~19FFFFh 1A0000h~1AFFFFh 1B0000h~1BFFFFh 1C0000h~1CFFFFh 1D0000h~1DFFFFh 1E0000h~1EFFFFh 1F0000h~1F7FFFh 1F8000h~1F9FFFh 1FA000h~1FBFFFh 1FC000h~1FFFFFh WORD MODE 00000h~07FFFh 08000h~0FFFFh 10000h~17FFFh 18000h~1FFFFh 20000h~7FFFFh 28000h~2FFFFh 30000h~37FFFh 38000h~3FFFFh 40000h~47FFFh 48000h~4FFFFh 50000h~57FFFh 58000h~5FFFFh 60000h~67FFFh 68000h~6FFFFh 70000h~77FFFh 78000h~7FFFFh 80000h~87FFFh 88000h~8FFFFh 90000h~97FFFh 98000h~9FFFFh A0000h~A7FFFh A8000h~AFFFFh B0000h~B7FFFh B8000h~BFFFFh C0000h~C7FFFh C8000h~CFFFFh D0000h~D7FFFh D8000h~DFFFFh E0000h~E7FFFh E8000h~EFFFFh F0000h~F7FFFh F8000h~FBFFFh FC000h~FCFFFh FD000h~FDFFFh FE000h~FFFFFh
2001-09-05 38/41
TC58FVT160/B160AFT/AXB-70,-10
(2) TC58FVB160A (bottom boot block)
BLOCK # BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BLOCK ADDRESS A19 A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 1 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x BLOCK SIZE (Kbytes/Kwords) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 ADDRESS RANGE BYTE MODE 0000h~3FFFh 4000h~5FFFh 6000h~7FFFh 8000h~FFFFh 10000h~1FFFFh 20000h~2FFFFh 30000h~3FFFFh 40000h~4FFFFh 50000h~5FFFFh 60000h~6FFFFh 70000h~7FFFFh 80000h~8FFFFh 90000h~9FFFFh A0000h~AFFFFh B0000h~BFFFFh C0000h~CFFFFh D0000h~DFFFFh E0000h~EFFFFh F0000h~FFFFFh 100000h~10FFFFh 110000h~11FFFFh 120000h~12FFFFh 130000h~13FFFFh 140000h~14FFFFh 150000h~15FFFFh 160000h~16FFFFh 170000h~17FFFFh 180000h~18FFFFh 190000h~19FFFFh 1A0000h~1AFFFFh 1B0000h~1BFFFFh 1C0000h~1CFFFFh 1D0000h~1DFFFFh 1E0000h~1EFFFFh 1F0000h~1EFFFFh WORD MODE 0000h~1FFFh 2000h~2FFFh 3000h~3FFFh 4000h~7FFFh 8000h~FFFFh 10000h~17FFFh 18000h~1FFFFh 20000h~27FFFh 28000h~2FFFFh 30000h~37FFFh 38000h~3FFFh 40000h~47FFFh 48000h~4FFFFh 50000h~57FFFh 58000h~5FFFFh 60000h~67FFFh 68000h~6FFFFh 70000h~77FFFh 78000h~7FFFFh 80000h~87FFFh 88000h~8FFFFh 90000h~97FFFh 98000h~9FFFFh A0000h~A7FFFh A8000h~AFFFFh B0000h~B7FFFh B8000h~BFFFFh C0000h~C7FFFh C8000h~CFFFFh D0000h~D7FFFh D8000h~DFFFFh E0000h~E7FFFh E8000h~EFFFFh F0000h~F7FFFh F8000h~FFFFFh
2001-09-05 39/41
TC58FVT160/B160AFT/AXB-70,-10
PACKAGE DIMENSIONS
Unit: mm
2001-09-05 40/41
TC58FVT160/B160AFT/AXB-70,-10
PACKAGE DIMENSIONS
Unit: mm
2001-09-05 41/41

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